1) Field of the Invention
This invention relates generally to the fabrication of high density semiconductor circuits and more particularly to a method for fabricating interconnections and conductors (e.g., wiring lines) for high density integrated circuits.
2) Description of the Prior Art
Semiconductor technologies have dramatically increased the circuit density on a chip. The miniaturized devices built in and on a semiconductor substrate are very closely spaced and their packing density has increased significantly. More recent advances in photolithographic techniques, such as phase-shifting masks, and self-aligning process steps have further reduced the device sized and increased circuit density. This has lead to ultra large scale integration (ULSI) with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With this improved integration, some circuit elements experience electrical limitations due to their down sizing.
One such circuit element experiencing electrical limitations is the array of storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field effect transistor (MOS-FET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. metallization in contact with the semiconductor substrate is called contact metallization. In MOS devices, polysilicon film and metal silicides have been the form of metallization used for gate and interconnection of MOS devices. Interconnection metallization, which interconnects thousands of MOSFET's or bipolar devices using fine line metal patterns, is generally the same as gate metallization.
The inability to further miniaturize the contact metallization and first level interconnections is a major obstacle in the miniaturization of DRAMs and other devices, such as MOS and Bipolar devices. The interconnect packing density in integrated circuits is limited by printing resolution and etching capability. Significant increase in the packing density requires more advanced costly stepper and plasma etcher equipment. Thus, the problems forming smaller first level contacts and first level interconnections must be solved to achieve higher packing density in a semiconductor memory devices.
U.S. Pat. No. 5,516,726 (Kim) shows conventional methods of forming metal layers and interconnects. U.S. Pat. No. 5,466,640 (Choi) shows a method of forming a plurality of metal lines densely packed using two photo masks. U.S. Pat. No. 5,444,015 (Aiken et al.) shows a method of forming interconnects by selective deposition of metal in insulating vias.
However, many of the prior art methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. Also, other process methods rely on etching to a predetermined etch depth which can be quite difficult to control in a manufacturing environment. For example, during plasma etching outgassing, virtual or real leaks, back streaming from pumps and loading effects, to name a few, can change the chemistry of the etching environment in the process chamber, making a calibrated etch time approach difficult to control. Therefore, it is very desirable to develop processes that are as simple as possible and also provide methods that do not require etches with critical depths.
There is a challenge to develop methods of manufacturing these interconnects and conductors that minimize the manufacturing costs and maximize the device yields. There is also a challenge to develop an interconnection process in which the interconnect size is not limited in size by the photolithographic techniques. In particular, there is a challenge to develop a method of forming more closely packed interconnects using conventional photolithography and etching equipment.